Integrated circuits (ICs) are growing in complexity and in the amount of circuitry that they integrate in a single product. In order to handle their complexity, their design is increasingly done in a modular fashion. Not only small design units such as standard library cells are reused, but also larger design modules often referred to as ‘cores’ are used and re-used as pre-designed components in ‘system-on-chip’ (SOC) design to ease the overall design integration effort. With the advent of 2.5D- and 3D-Stacked ICs (SICs) also the manufacturing is moving to a modular approach, with benefits in performance, power dissipation, and yield.
As the IC manufacturing process consists of many high-precision and hence defect-prone steps, raw manufacturing yields are unacceptably low for IC users. Consequently, every IC needs to be tested for manufacturing defects before it is being shipped to the customer. Testing of large and complex (2D) SOCs, 2.5D-SICs, and 3D-SICs is increasingly done in a modular fashion as well. In this modular test approach, the various design modules (e.g., stacked dies, embedded cores) are tested as stand-alone units. In addition, the interconnect wiring and logic in between the various modules are tested. A modular test approach has benefits for both test development and test application. Different circuit structures (e.g., digital logic, DRAM, SRAM, analog, FPGA) exhibit different defect behavior and hence may require dedicated test pattern generation; this is enabled by a modular test approach. Black-boxed third-party Intellectual Property (IP) cores require a modular approach, as the design content of the IP core is not available to the system-chip integrator, and hence he/she needs to work with test patterns generated by the core provider. A modular test approach also allows for Divide-and-Conquer test generation, which reduces the test development time as well as the test application time. For 2.5D- and 3D-SICs, additional benefits of a modular test approach include yield monitoring, first-order fault diagnosis, and flexible test scheduling (inclusion, exclusion, and re-ordering of module tests) on the test floor; the latter feature is especially attractive when manufacturing yields mature over time.
Modular testing requires an on-chip Design-for-Test (DfT) architecture, in which the various modules are equipped with dedicated test circuitry. This test circuitry provides test controllability and observability at the module's I/Os. For embedded cores, a standardized test wrapper has been proposed pursuant to IEEE Std 1500. For 2.5D and 3D-SICs, a 3D-DfT architecture based on die-level wrappers is currently being considered for standardization by the IEEE 3D-Test Working Group as IEEE P1838. A modular DfT architecture allows one or multiple Modules-Under-Test (MUTs) to be tested simultaneously.
In general, manufacturing defects can only be detected by switching the circuit. As there often is a need to minimize the test application time, test generation focuses on getting high fault coverage with a small number of test patterns which results in a high switching activity of the circuit in a test mode. Whereas in a functional mode of operation perhaps on average only 10% of the sequential storage elements (e.g., flip-flops) are switching from one clock cycle to the next, during testing there can easily be 30% to 50% switching activity per clock cycle. The power grid of a chip, which is typically dimensioned for functional operation only, might not be able to handle the large switching activity during test. Consequently, an IC might fail a test unjustifiably (“false reject”) or it might be permanently damaged due to excessive switching activity (“brown-out”), both resulting in lower yields. One counter-measure is to lower the test frequency, but this inhibits detection of timing defects (“at-speed testing”) and increases the test application time. Another counter-measure is Power-Aware ATPG (Automatic Test Pattern Generation), in which patterns are generated such that the switching activity of the test is explicitly reduced below a user-defined maximum. For example, exploiting the many “don't care” bits in ATPG patterns with the so-called “repeat fill” strategy, the switching activity during test can be significantly reduced without increasing the test pattern count. In order to achieve really low switching activity levels, it will typically be required to increase the test pattern count.
The above-described counter-measures against false rejects and “brown-out” pertain to the actual Module-Under-Test (MUT) itself. However, in a modular test set-up, there is concern not only about the level of switching activity in the MUT, but also about the level of switching activity in the modules neighboring to the MUT. If those neighbor modules switch too much, even if they are momentarily not tested themselves but only serve to transport test stimuli and/or responses to the MUT(s), the test result for the MUT(s) can still be affected. A common counter-measure is to quiet the neighboring modules, e.g., by switching off their scan chains. Unfortunately, although this solution addresses the problem of false rejects or “brown-out”, it might provide a too-optimistic test environment for the MUT(s) and consequently lead to (even more expensive) test escapes (“false positives”).